2 Months project work
20th July 2020
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MCA and BCA
An integration of high end laboratory facilities, globally recognized domains and industry oriented expertise.
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Hardware Modeling Overview, Introduction to Verilog, Modules and Ports
Different Modeling styles, Test benches, Data Types, Operators, Verilog Coding for Combinational and Sequential Circuits, Procedural Blocks
Finite State Machines Coding, Synthesis, Tasks and Functions, Project
Introduction to System Verilog, Test benches, Data Types, Operators, Procedural Blocks
System Verilog Coding for Combinational and Sequential Circuits,
System Verilog Coding for Finite State Machines , Synthesis, project, verification using System Verilog
Matalb / Simulink.
Design of Low-Power High-Performance 2–4 and 4–16 Mixed-Logic Line Decoders
An Architecture for 32-bit Energy-Efficient Wallace Tree Carry Save Adder
FPGA Implementation of Combined S-Box and InvS-Box of AES
Design of Power and Area Efficient Approximate Multipliers
Design and Implementation of a 5-Bit Flash ADC for Education
Hardware Architecture for 2D Gaussian Filtering of HD Images on Resource Constrained Platforms